In power integrated circuits, there is frequently a need for several power devices to be formed on a single chip. One such application is an H-bridge driver circuit for motor control. In order to reduce the cost and increase the producibility of an integrated circuit having multiple power devices, the size of each power device must be minimized.
The size of a power device is dictated mainly by the need for a given low on-resistance (R.sub.on). The minimum on-resistance per unit area is normally associated with a vertical MOS device, as opposed to a lateral device. In such devices, the gate is formed on a semiconductor surface, the source is formed in a doped region of an opposite conductivity type, and the drain contact is located at the bottom of the chip. Hence, the substrate acts as the drain. When a voltage is applied to the gate, a channel is formed through the doped region, and current may flow from surface source to substrate drain.
Vertical MOS devices provide several advantages over their lateral counterparts. First, the channel width per unit area, and hence, current handling capability is higher. Further, the drain contact is at the bottom in the vertical transistors and the metal scheme required to handle high currents is simplified.
Unfortunately, in a bulk process, if more than one device is integrated on a chip using bottom drains, all drains are inherently connected together. This fairly limits the complexity of a circuit using these devices. In one proposed device, vertical transistors are set in polysilicon. This structure somewhat reduces the coupling between drains, but does not isolate the drains to a desirable degree.
Therefore, a need has arisen to provide a vertical transistor which may be isolated from other devices.